COPROCESSOR FOR OUT-OF-ORDER LOADS

摘要

Systems and methods for implementing certain load instructions, such as vector load instructions by cooperation of a main processor and a coprocessor. The load instructions which are identified by the main processor for offloading to the coprocessor are committed in the main processor without receiving corresponding load data. Post-commit, the load instructions are processed in the coprocessor, such that latencies incurred in fetching the load data are hidden from the main processor. By implementing an out-of-order load data buffer associated with an in-order instruction buffer, the coprocessor is also configured to avoid stalls due to long latencies which may be involved in fetching the load data from levels of memory hierarchy, such as L2, L3, L4 caches, main memory, etc.

主权项

1. A method of operating a processing system, the method comprising:
identifying a first load instruction in a main processor for offloading to a coprocessor; committing the first load instruction in the main processor without receiving, by the main processor, first load data for satisfying the first load instruction; and offloading processing of the first load instruction to the coprocessor after the committing in the main processor.