| 摘要 |
A highly reliable and low computational load heart rhythm recognition circuit and method applicable in a wearable device. The circuit comprises at least one software filter, one normally open software phase-locked loop, at least one backup software phase-locked loop, and at least one control logical unit K. Each backup software phase-locked loop is connected in parallel to the normally open software phase-locked loop. A signal output end of the software filter is connected respectively to the normally open software phase-locked loop and the backup software phase-locked loop. The normally open software phase-locked loop and each backup software phase-locked loop respectively comprise a heart rhythm signal output end and a frequency overflow flag output end. The heart rhythm signal output ends and the frequency overflow flag output ends respectively are connected to control logical unit K. The circuit has a lowered requirement on the signal-to-noise ratio of a signal, great robustness, and a broad recognition range. The method has an extremely low requirement on a processor, low power consumption, high reliability, and low computational load and is applicable in a wearable device. |
