Cross-Coupled Thyristor SRAM Semiconductor Structures and Methods of Fabrication

摘要

A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby.

主权项

1. A first semiconductor structure for a cross-coupled pair of first type and opposite type bipolar transistors comprising:
a first conductivity type semiconductor substrate having an upper surface; an insulating region extending into the substrate to surround a first portion of the upper surface of the substrate; a buried layer of opposite conductivity type to the first conductivity type disposed in the substrate beneath the first portion of the upper surface, the buried layer and the insulating region together providing a tub of semiconductor material electrically isolated from remaining portions of the substrate; a connecting region of first conductivity type extending from the upper surface of the substrate to the buried layer to provide an electrical connection to the buried layer; a shallow well region of opposite conductivity type extending from the upper surface into the substrate over a second portion of the upper surface smaller than the first portion, the shallow well region not extending to the buried layer; a first conductivity type region adjacent the upper surface and extending into the tub outside the first portion of the upper surface, and not in contact with the buried layer to provide an electrical connection to the tub; a field effect transistor gate disposed over the shallow well region; a first conductivity type region disposed adjacent a first side of the field effect transistor gate; an opposite conductivity type region disposed adjacent a second side of the field effect transistor gate; and wherein:
the buried layer provides an emitter of the first type bipolar transistor;the first conductivity type tub provides a base of the first type bipolar transistor;the shallow well provides a collector of the first type bipolar transistor and a base for the opposite type bipolar transistor; andthe first conductivity type region disposed adjacent one side of the field effect transistor gate electrode provides an emitter region for the opposite type bipolar transistor.