IMPLEMENTATIONS OF, AND METHODS OF USE FOR A PATTERN MEMORY ENGINE APPLYING ASSOCIATIVE PATTERN MEMORY FOR PATTERN RECOGNITION

摘要

Computer-readable storage memory may include a) input memory having addressable blocks of random access memory storing an input data pattern, b) pattern input address memory having addressable blocks of random access memory, each of the addressable blocks storing a predetermined address of the input memory, c) current state address memory comprising a block of random access memory storing a current state address, and d) at least one next state memory having addressable blocks of random access memory, each of the addressable blocks storing predetermined data determining a next state address. The pattern input address memory and the at least one next state memory may each be sized with at least a number of addressable blocks as a maximum state address storable in the current state address memory. The current state address may index an addressable block of the pattern input address memory and the at least one next state memory.

主权项

1. A computer-readable storage memory comprising:
input memory comprising addressable blocks of random access memory, the input memory storing an input data pattern; pattern input address memory comprising addressable blocks of random access memory, each of the addressable blocks storing a predetermined address of the input memory; current state address memory comprising a block of random access memory storing a current state address; and at least one next state memory comprising addressable blocks of random access memory, each of the addressable blocks storing predetermined data for determining a next state address to store in the current state address memory; wherein the pattern input address memory and the at least one next state memory are each sized with at least a number of addressable blocks as a maximum state address storable in the current state address memory; and wherein the current state address indexes an addressable block of the pattern input address memory and the at least one next state memory.