Six-Transistor SRAM Circuits and Methods of Operation

摘要

A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

主权项

1. In an integrated circuit having at least one logic circuit operating within a MOSFET logic circuit range and a plurality of memory cells arranged in an array interconnected by a plurality of complementary bit line pairs and a plurality of word lines, each memory cell in the array connected a complementary bit line pair and a word line, each memory cell comprising:
a pair of cross-coupled thyristors, each thyristor having first and second semiconductor regions intermediate an anode and a cathode, a first intermediate region of one thyristor connected to the second intermediate region of the other thyristor and a second intermediate region of the one thyristor connected to the first intermediate region of the other thyristor, each thyristor having an anode connected to a first supply voltage and a cathode connected to a second supply voltage; and a pair of select transistors, each select transistor connected between one of the complementary bit line pair, and a first intermediate region of one thyristor and a second intermediate region of the other thyristor, each select transistor having a control terminal connected to the word line; wherein the memory cell has regions electrically biased so that voltage swings on the complementary bit line pair and the word line, operating within a magnitude of the MOSFET logic circuit range, are sufficient to read and write the memory cell.