发明名称 Method and Apparatus For Deterministic Translation Lookaside Buffer (TLB) Miss Handling
摘要 An apparatus and method are described for translation lookaside buffer (TLB) miss handling. For example, one embodiment of a processor comprises: a translation lookaside buffer (TLB) to store virtual-to-physical address translations; a page miss handler (PMH) to process TLB misses when a desired virtual-to-physical address translation is not present in the TLB; and a compressed page table to be managed by the PMH, the compressed page table to store specified portions of page tables, wherein in response to a TLB miss for a first address translation, the PMH is to check the compressed page table to determine if a page table entry corresponding to the first address translation is stored therein and, if so, to provide the first address translation from the compressed page table.
申请公布号 US2016092371(A1) 申请公布日期 2016.03.31
申请号 US201414498321 申请日期 2014.09.26
申请人 INTEL CORPORATION 发明人 SHANBHOGUE VEDVYAS
分类号 G06F12/10 主分类号 G06F12/10
代理机构 代理人
主权项 1. A processor comprising: a translation lookaside buffer (TLB) to store virtual-to-physical address translations; a page miss handler (PMH) to process TLB misses when a desired virtual-to-physical address translation is not present in the TLB; and a compressed page table to be managed by the PMH, the compressed page table to store specified portions of page tables, wherein in response to a TLB miss for a first address translation, the PMH is to check the compressed page table to determine if a page table entry corresponding to the first address translation is stored therein and, if so, to provide the first address translation from the compressed page table.
地址 SANTA CLARA CA US