Hybrid cache state and filter tracking of memory operations during a transaction

摘要

In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a cache memory to store a plurality of cache lines, each including a tag portion, a data portion, a write-set field to store a write-set indicator to indicate whether data stored in the data portion has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators comprising a bit for each particular thread of a plurality of threads to indicate whether the particular thread of the plurality of threads has read the data stored in the data portion of the cache line before the transaction has committed; and a compression filter associated with the cache memory, the compression filter including a first filter storage to store a representation of a cache line address of a cache line read by a first thread of the plurality of threads before the transaction has committed.