Dynamic data caches, decoders and decoding methods

摘要

Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines.

主权项

1. A cache access circuit comprising:
a data input/output line; a cache line; a first transistor having a source/drain terminal coupled to the data input/output line, wherein the first transistor is configured to receive a first select signal at its gate terminal; and a second transistor having a first source/drain terminal coupled to the source/drain terminal of the first transistor and a second source/drain terminal coupled to the cache line, wherein the second transistor is configured to receive a second select signal at its gate terminal; wherein the first select signal is configured to select a group of bytes, and the second select signal is configured to select a particular byte within the group of bytes.