HARDWARE TIMER BASED MECHANISM TO CHECK INTERRUPT DISABLED DURATION

摘要

In one embodiment, a timer apparatus is configured to time a duration in which interrupts are disabled on a processor. The apparatus includes an input to receive a start signal indicating that an interrupt on a processor is disabled, a counter to determine the duration in which interrupts are disabled, and an output to signal a timer event based on the counter. The processor may be configured to trigger a hardware exception in response to the timer event signal. When the interrupts are re-enabled on the processor, the counter of the apparatus may be disabled.

主权项

1. An apparatus comprising:
an input to receive a start signal, the start signal to indicate an interrupt on a processor is disabled; a counter to determine an interrupt disabled duration; and an output to signal a timer event based on the counter.