发明名称 |
MECHANISM FOR FACILITATING COST-EFFICIENT AND LOW-LATENCY ENCODING OF VIDEO STREAMS |
摘要 |
A mechanism for facilitating cost-efficient and low-latency video stream encoding for limited channel bandwidth is described. In one embodiment, an apparatus includes a source device having an encoding logic. The encoding logic may include a first logic to receive a video stream having a plurality of video frames. The video stream is received frame-by-frame. The encoding logic may further include a second logic to determine an input data rate relating to a first current video frame of the plurality of video frames received at the encoding mechanism, and a third logic to generate one or more zero-delta frames based on the input data rate, and allocate the one or more zero-delta frames to one or more first video frames of the plurality of video frames subsequent to the first current video frame. |
申请公布号 |
EP2845383(A4) |
申请公布日期 |
2016.03.23 |
申请号 |
EP20130784901 |
申请日期 |
2013.03.20 |
申请人 |
SILICON IMAGE, INC. |
发明人 |
YANG, WOOSEUNG;YI, JU HWAN;KIM, YOUNG IL;CHOI, HOON |
分类号 |
H04N19/172;H04N19/107;H04N19/132;H04N19/146;H04N19/154;H04N19/164 |
主分类号 |
H04N19/172 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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