发明名称 不揮発性メモリ、電子装置及び検証方法
摘要 A gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to a memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to a reference cell array is included. An electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line.
申请公布号 JP5891918(B2) 申请公布日期 2016.03.23
申请号 JP20120090226 申请日期 2012.04.11
申请人 株式会社ソシオネクスト 发明人 田仲 研吾
分类号 G11C16/02;G11C16/04;G11C16/06 主分类号 G11C16/02
代理机构 代理人
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