发明名称 |
Path isolation in a memory device |
摘要 |
Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed. |
申请公布号 |
US9293202(B2) |
申请公布日期 |
2016.03.22 |
申请号 |
US201414579885 |
申请日期 |
2014.12.22 |
申请人 |
INTEL CORPORATION |
发明人 |
Castro Hernan A. |
分类号 |
G11C11/00;G11C13/00;G11C16/06;G11C7/12;G11C7/10;G11C13/02 |
主分类号 |
G11C11/00 |
代理机构 |
Schwabe Williamson & Wyatt PC |
代理人 |
Schwabe Williamson & Wyatt PC |
主权项 |
1. An apparatus comprising:
a memory cell of a memory device; a bit-line electrode coupled with a bit-line; a word-line electrode coupled with a word-line; and write circuitry coupled to the word-line electrode, the write circuitry to perform a write operation of the memory cell, wherein the apparatus is to provide a capacitance of the word-line electrode that is lower than a capacitance of the bit-line electrode, and a potential of the word-line electrode that is lower than a potential of the bit-line electrode. |
地址 |
Santa Clara CA US |