Level shift circuit utilizing resistance in semiconductor substrate

摘要

An apparatus such as a level shift circuit includes a first signal output device configured to output a first level shifting signal, a second signal output device configured to output a second level shifting signal, and first and second detector devices. The level shifting signals are to control an output switching element of a high potential side of an output device that includes a power source and a load. The first and second detector devices are respectively configured to compare the first and second level shifting signals to a reference signal and output respective first and second comparison result signals. The first and second comparison result signals are configured to at least partly control switching of the first and second level shifting signals based at least in part on the presence of a parasitic resistance.

主权项

1. An apparatus, comprising:
a first signal output device configured to output a first level shifting signal and including a first resistance; a second signal output device configured to output a second level shifting signal and including a second resistance; wherein the first level shifting signal and the second level shifting signal are to control an output switching element of a high potential side of an output device comprising a power source and a load; a first detector device configured to compare the first level shifting signal to a reference signal and output a first comparison result signal to a first switching element coupled to the first resistance; and a second detector device configured to compare the second level shifting signal to the reference signal and output a second comparison result signal to a second switching element coupled to the second resistance; wherein
the first comparison result signal and second comparison result signals are configured to at least partly control switching of the first switching element and the second switching element, and each of the resistance and the second resistance is a parasitic resistance in a semiconductor substrate included in the apparatus.