发明名称 SEMICONDUCTOR DEVICE
摘要 According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.
申请公布号 US2016079436(A1) 申请公布日期 2016.03.17
申请号 US201514952156 申请日期 2015.11.25
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 NISHIMURA Jun;YASUTAKE Nobuaki;OKAMURA Takayuki
分类号 H01L29/786;H01L29/423;H01L27/24 主分类号 H01L29/786
代理机构 代理人
主权项 1. A semiconductor device comprising: a first line configured to extend in a first direction along a surface of a semiconductor substrate; and a first transistor configured to be disposed above the first line, the first transistor including: a first semiconductor region which is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line;a third semiconductor region which is provided, in the second direction, on an opposite side of the semiconductor substrate with respect to the first semiconductor region in the first semiconductor layer;a second semiconductor region which is provided, in the second direction, between the first semiconductor region and the third semiconductor region in the first semiconductor layer;a first gate insulating film which covers a first side face of the second semiconductor region;a first gate electrode which covers the first side face of the second semiconductor region through the first gate insulating film;a second line configured to be connected to an upper face of the first semiconductor layer and to extend in the second direction;a plurality of third lines configured to extend along the surface of the semiconductor substrate and to intersect with the second line above the first transistor; anda plurality of memory cells configured to be disposed at positions where the second line and the plurality of third lines intersect,a face of the first gate electrode which abuts on the first gate insulating film being curved so that a portion on a side of the first semiconductor region is spaced apart from the first semiconductor layer.
地址 Minato-ku JP