ENHANCED PATTERNED WAFER GEOMETRY MEASUREMENTS BASED DESIGN IMPROVEMENTS FOR OPTIMAL INTEGRATED CHIP FABRICATION PERFORMANCE

摘要

Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.