| 摘要 |
The invention relates to a circuit arrangement and to a method for testing same. A circuit arrangement is provided that comprising a plurality of functional units which are coupled by at least one streaming data bus. Each of the functional units comprises a plurality of hardware modules and a switch matrix. At least one of the streaming data busses is provided with a data width of at least that of the widest hardware module of any of the functional units of the circuit arrangement. The switch matrices are configurable to establish a streaming data path between and through the plurality of functional units which is used as a test link for any of the hardware modules of the circuit arrangement. The invention provides for non-intrusive real-time tracing in SoCs with a minimum of additional hardware resources and at low cost in terms of die size and power consumption. |
