发明名称 積層セラミックキャパシタ及び積層セラミックキャパシタの回路基板実装構造
摘要 There is provided a multilayered ceramic capacitor, including a ceramic body, an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body while having the dielectric layer therebetween, to form capacitance; upper and lower cover layers formed above and below the active layer; first and second external electrodes covering both end surfaces of the ceramic body; a plurality of first and second dummy electrodes extended from the first and second external electrodes; and a plurality of piezoelectric members connecting the first internal electrode and the first dummy electrode or the second internal electrode and the second dummy electrode, inside the active layer, the piezoelectric members having a higher dielectric constant than the dielectric layer.
申请公布号 JP5886222(B2) 申请公布日期 2016.03.16
申请号 JP20130028681 申请日期 2013.02.18
申请人 サムソン エレクトロ−メカニックス カンパニーリミテッド. 发明人 アン・ヨン・ギュ;パク・フン・キル;キム・ド・ヨン;パク・サン・ス;パク・ミン・チョル
分类号 H01G4/12;H01G4/30 主分类号 H01G4/12
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