Method and apparatus for floating or applying voltage to a well of an integrated circuit

摘要

In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

主权项

1. An integrated circuit, comprising:
a semiconductor substrate; an n-well in the substrate having a range of n-well depths relative to a surface plane including a deepest n-well depth relative to the surface plane; a device in the n-well having at least one terminal with a range of n-well terminal depths relative to the surface plane including a deepest n-well terminal depth relative to the surface plane shallower, relative to the surface plane, than the deepest n-well depth relative to the surface plane; a p-well in the substrate having a range of p-well depths relative to the surface plane including a deepest p-well depth relative to the surface plane; a device in the p-well having at least one terminal with a range of p-well terminal depths relative to the surface plane including a deepest p-well terminal depth relative to the surface plane shallower, relative to the surface plane, than the deepest p-well depth relative to the surface plane; and biasing circuitry providing all bias voltages required by the device in the n-well and the device in the p-well for operation, wherein during operation of the device in the n-well and the device in the p-well: (i) the biasing circuitry applies a bias voltage arrangement to the device in the n-well and the device in the p-well, (ii) no well bias voltage is applied by the biasing circuitry to the n-well, and (iii) no well bias voltage is applied by the biasing circuitry to the p-well, wherein the n-well and the p-well are physically connected directly to each other along a range of shared well depths from the surface plane to an intermediate plane in the substrate deeper than the surface plane.