Low leakage shadow latch-based multi-threshold CMOS sequential circuit

摘要

Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit.

主权项

1. A multi-threshold CMOS sequential circuit, comprising:
a first latch circuit formed of transistors having threshold voltages in a first range and powered from a switchable voltage node to provide a primary data path storing at least one data bit during active mode operation of the sequential circuit; and a second latch circuit, comprising:
inverters formed of transistors selectively powered from a continuous voltage node and having threshold voltages in a second range higher than the first range, the inverters of the second latch circuit selectively operative for low-power retention mode operation of the sequential circuit to latch the at least one data bit transferred from the first latch circuit,a transfer gate formed of transistors having threshold voltages in the second range and providing a data transfer path between the first and second latch circuits during transitions from active to low-power retention mode and vice versa, the transmission gate operative to disconnect the first and second latch circuits from one another during both active mode and low-power retention mode operation of the sequential circuit, anda second switching circuit selectively operative to disconnect the inverters of the second latch circuit from the continuous voltage node during active mode operation of the sequential circuit.