Instruction set architecture with opcode lookup using memory attribute

摘要

A method decodes instructions based in part on one or more decode-related attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a decode of an instruction stored in a page of memory, such that one or more attributes associated with the page in the data structure may be used to control how that instruction is decoded.

主权项

1. A method of executing instructions from an instruction set architecture in a processing unit, the method comprising:
in response to receiving an instruction in an instruction stream, accessing a decode-related attribute in a memory address translation data structure, wherein the instruction is associated with an address at which the instruction is stored in an address space, wherein the memory address translation data structure is used to perform memory address translation for instructions in the instruction stream, and wherein the decode-related attribute is accessed using at least a portion of the address; and decoding at least a portion of an opcode for the instruction using the decode-related attribute, wherein decoding includes accessing an opcode data structure using the decode-related attribute to determine the at least a portion of the opcode, wherein the opcode data structure comprises a table storing a plurality of opcodes, and wherein the decode-related attribute includes at least a portion of an index used to select an opcode from among the plurality of opcodes.