| 摘要 |
The present invention relates to a shift register, capable of reducing a circuit area by simplifying a logic circuit, and a display device using the same. The shift register includes a plurality of stages where forward scan and backward scan are selectively performed. Each stage uses a first, a second, a third, and a fourth clock. Each stage includes: a pull-up transistor which generates the first clock as output by control of a control node; a pull-down transistor which generates gate-off voltage as output by control of the third clock; a first transistor which sets and resets the control node during the forward scan and resets the control node during the backward scan by using an output signal of a previous stage by the fourth clock; and a second transistor which sets and resets the control node during the backward scan and resets the control node during the forward scan by using an output signal of a next stage by control of the second clock. |
