DISPLAY DEVICE, DISPLAY PANEL DRIVER, AND IMAGE DATA SIGNAL TRANSMISSION METHOD

摘要

For each unit transmission block having a pixel data block including at least one pixel data piece, clock data is added contiguously to a head of the pixel data block. If no data transition has occurred at a boundary between the clock data and the pixel data block, logic inversion is performed on the pixel data piece. Thereafter, a transmission image data signal in which unit transmission blocks, each constituted by adding an inversion flag immediately before the clock data, are consecutively arranged is transmitted to a display panel driver. The driver generates a clock signal on the basis of the clock data included in the received signal and takes in the pixel data piece or the resultant obtained by inverting the logic level of this pixel data piece in accordance with the clock signal on the basis of the inversion flag.

主权项

1. A display device for displaying an image on the basis of input image data including a sequence of pixel data pieces each indicating a luminance level of a pixel, the display device comprising:
a driver for applying pixel driving voltages to a plurality of data lines formed in a display panel; and a control unit for generating a transmission image data signal in which unit transmission blocks, each having a pixel data block including at least one of the pixel data pieces in the sequence of the pixel data pieces in the input image data, are consecutively arranged and transmitting the transmission image data signal to the driver, wherein the control unit includes:
a first processing unit for adding clock data contiguously to a head of the pixel data block for each of the unit transmission blocks;a second processing unit for determining whether data transition has occurred at a boundary between the clock data and the pixel data block;a third processing unit for inverting a logic level of the pixel data piece included in the pixel data block if it is determined that the data transition has not occurred; anda fourth processing unit for adding an inversion flag that indicates whether logic level inversion processing has been performed on the pixel data piece included in the pixel data block immediately before the clock data, and the driver includes:
a clock generating unit for generating a clock signal phase-synchronized with a rear edge of the clock data included in the transmission image data signal received;a data take-in unit for taking in and outputting resultant obtained by inverting a logic level of the pixel data piece included in the transmission image data signal received in accordance with the clock signal if the inversion flag included in the transmission image data signal received indicates that the inversion processing has been performed, and taking in and outputting the pixel data piece in accordance with the clock signal if the inversion flag indicates that the inversion processing has not been performed; anda gradation voltage generating unit for converting the pixel data pieces output from the data take-in unit to the pixel driving voltages.