| 发明名称 |
Memory System Configured to Avoid Memory Access Hazards for LDPC Decoding |
| 摘要 |
Techniques are disclosed relating to resolving memory access hazards. In one embodiment, an apparatus includes a memory and circuitry coupled to or comprised in the memory. In this embodiment, the circuitry is configured to receive a sequence of memory access requests for the memory, where the sequence of memory access requests is configured to access locations associated with entries in a matrix. In this embodiment, the circuitry is configured with memory access constraints for the sequence of memory access requests. In this embodiment, the circuitry is configured to grant the sequence of memory access requests subject to the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests. |
| 申请公布号 |
US2016070498(A1) |
申请公布日期 |
2016.03.10 |
| 申请号 |
US201414522869 |
申请日期 |
2014.10.24 |
| 申请人 |
National Instruments Corporation |
发明人 |
Ly Tai A.;Mhaske Swapnil D.;Kee Hojin;Arnesen Adam T.;Uliana David C.;Petersen Newton G. |
| 分类号 |
G06F3/06;H03M13/11;G06F11/10 |
主分类号 |
G06F3/06 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus, comprising:
a memory; and first circuitry coupled to or comprised in the memory and configured to:
receive a sequence of memory access requests for the memory, wherein the sequence of memory access requests is configured to access locations associated with entries in a matrix, wherein the first circuitry is configured with memory access constraints for the sequence of memory access requests; andgrant the sequence of memory access requests subject to the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests. |
| 地址 |
Austin TX US |
