Semiconductor device including gate structure for threshold voltage modulation in transistors and method for fabricating the same

摘要

A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first gate dielectric layer and a first work function layer that is disposed over the first gate dielectric layer and contains aluminum, over the PMOS region of the substrate, forming a second stack layer including a second gate dielectric layer, a threshold voltage modulation layer that is disposed over the second gate dielectric layer and contains lanthanum, and a second work function layer that is disposed over the threshold voltage modulation layer, over the NMOS region of the substrate, and annealing the first stack layer and the second stack layer, thereby forming a first dipole-interface by diffusion of the aluminum in the first gate dielectric layer and a second dipole-interface by diffusion of the lanthanum in the second gate dielectric layer, respectively.

主权项

1. A method for fabricating a semiconductor device, comprising:
forming an NMOS region and a PMOS region in a substrate; forming a gate dielectric layer over the substrate; forming a first work function layer that contains aluminum over the gate dielectric layer; forming a reaction preventing layer consisting of polysilicon over the first work function layer; selectively removing the reaction preventing layer and the first work function layer from the NMOS region; forming a threshold voltage modulation layer that contains lanthanum over the remaining reaction preventing layer of the PMOS region and the gate dielectric layer of the NMOS region; forming a second work function layer over the threshold voltage modulation layer; and annealing, thereby forming a first dipole-interface by diffusion of the aluminum into the gate dielectric layer of the PMOS region and a second dipole-interface by diffusion of the lanthanum into the gate dielectric layer of the NMOS region, respectively, wherein the remaining reaction preventing layer is formed between the first work function layer and the threshold voltage modulation layer over the PMOS region.