发明名称 |
Control scheme for current balancing between parallel bridge circuits |
摘要 |
A control scheme for reducing current imbalance between parallel bridge circuits in a power converter system is provided. The power converter can include a plurality of bridge circuits coupled in parallel to increase the output power capability of the power system. The parallel bridge circuits can be controlled pursuant to a control scheme for reducing current imbalance between the parallel bridge circuits. In particular, a pulse test can be performed in which a pulse is applied to each of the plurality of bridge circuits. The switch timing of the switching elements responsive to the pulse can be measured and analyzed to determine a timing difference adjustment for one or more of the switching elements of the plurality of bridge circuits. The timing difference adjustment can be stored and used to adjust all subsequent switching events in the parallel bridge circuits. |
申请公布号 |
US9281761(B2) |
申请公布日期 |
2016.03.08 |
申请号 |
US201313744948 |
申请日期 |
2013.01.18 |
申请人 |
General Electric Company |
发明人 |
Wagoner Robert Gregory;Smith David |
分类号 |
H02M3/158;H02M7/493;H02M7/5387;H02M7/48 |
主分类号 |
H02M3/158 |
代理机构 |
Dority & Manning, P.A. |
代理人 |
Dority & Manning, P.A. |
主权项 |
1. A control method for reducing current imbalance between a plurality of bridge circuits in a multi-phase power converter, the plurality of bridge circuits being coupled in parallel for a same phase of the multi-phase power converter, the control method comprising:
applying a pulse as part of a pulse test to each of the plurality of bridge circuits coupled in parallel for the same phase of the power converter, each of the plurality of bridge circuits comprising at least one switching element; determining a timing difference between the parallel bridge circuits responsive to the pulse applied during the pulse test, the timing difference determined based on a time it takes for each switching element to perform a switching operation responsive to the pulse; analyzing the timing difference between the parallel bridge circuits to determine a timing difference adjustment for one or more of the switching elements of the plurality of bridge circuits, the timing difference adjustment comprising a timing offset to reduce the timing difference between the parallel bridge circuits; generating one or more control commands based at least in part on the timing difference adjustment; and controlling operation of the plurality of bridge circuits based at least in part on the one or more control commands. |
地址 |
Schenectady NY US |