发明名称 LEAD FRAME FOR INTEGRATED CIRCUIT
摘要 <p>PURPOSE:To lower the resistance of a wiring material for an integrated-circuit sealing package, and to improve characteristics such as the switching rate of a packaged integrated circuit by composing electrode wirings for the integrated-circuit sealing package and a lead frame of a superconductive material such as yttrium, barium, a copper oxide, etc. CONSTITUTION:Superconductive wirings 3 acquired by printing and baking the paste of yttrium, barium and a copper oxide are formed extending over the outside from the inside of a ceramic substrate 1, and an IC chip 7 is stuck to the substrate with paste, etc., into a package, in which the superconductive wirings 3 and superconductive leads 4 consisting of yttrium, barium and the copper oxide are pasted with superconductive paste 5 made up of yttrium, barium and copper oxide paste and baked, while pad metals 6 and wires 8 covered with a metal are assembled onto the surfaces of the superconductive wirings 3 in the package, and sealed with a cap 2. Accordingly, wiring resistance is reduced extremely, and the switching rate, etc., of a sealed integrated circuit are not decreased by sealing.</p>
申请公布号 JPS64754(A) 申请公布日期 1989.01.05
申请号 JP19870155686 申请日期 1987.06.23
申请人 SEIKO EPSON CORP 发明人 IWAMATSU SEIICHI
分类号 H01L39/06;H01L23/50 主分类号 H01L39/06
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