Charge compensation structure and manufacturing therefor

摘要

A charge-compensation semiconductor device includes a semiconductor body including a first surface, a second surface arranged opposite to the first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, a drain region of a of a first conductivity type extending to the second surface, an active area, and a peripheral area arranged between the active area and the edge, a source metallization arranged on the first surface, and a drain metallization arranged on the drain region and in Ohmic contact with the drain region. In a vertical cross-section substantially orthogonal to the first surface the charge-compensation semiconductor device further includes: an equipotential region in Ohmic contact with the drain metallization and arranged in the peripheral area and next to the first surface, a low-doped semiconductor region arranged in the peripheral area and having a first concentration of dopants, and a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area. The first pillar regions having a second concentration of dopants of the first conductivity type higher than the first concentration and are in Ohmic contact with the drain region. The second pillar regions are of a second conductivity type and in Ohmic contact with the source metallization. At least one of an outermost of the first pillar regions and an outermost of the second pillar regions forms an interface with the low-doped semiconductor region. A horizontal distance between the interface and the equipotential region divided by a vertical distance between the first surface and the drain region is in a range from about 0.5 to about 3.

主权项

1. A charge-compensation semiconductor device, comprising:
a rated breakdown voltage; a semiconductor body comprising a first surface, an edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, and a peripheral area arranged between the active area and the edge; a source metallization arranged on the first surface; and a drain metallization arranged opposite to the source metallization,in a vertical cross-section substantially orthogonal to the first surface the semiconductor body further comprising:
an intrinsic semiconductor region arranged in the peripheral area; and a plurality of first pillar regions alternating with second pillar regions in the active area and the peripheral area, the first pillar regions having a higher doping concentration than the intrinsic semiconductor region, the first pillar regions being in Ohmic contact with the drain metallization, the second pillar regions of the active area being in Ohmic contact with the source metallization via respective body regions having a higher doping concentration than the second pillar regions, at least a majority of the second pillar regions of the peripheral area adjoining a connecting region which is of the same conductivity type as the second pillar regions and has a lower doping concentration than an adjoining outermost of the body regions, between adjacent first pillar regions and second pillar regions a respective pn-junction being formed, at least one of an outermost of the first pillar regions and an outermost of the second pillar regions forming an interface with the intrinsic semiconductor region at a horizontal position where a voltage at the first surface is at least about a fifth of the rated breakdown voltage when the rated breakdown voltage is applied between the source metallization and the drain metallization.