发明名称 U-SHAPED COMMON-BODY TYPE CELL STRING
摘要 A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.
申请公布号 US2016064410(A1) 申请公布日期 2016.03.03
申请号 US201514938259 申请日期 2015.11.11
申请人 CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. 发明人 RHIE Hyoung Seub
分类号 H01L27/115;G11C16/14 主分类号 H01L27/115
代理机构 代理人
主权项 1. A NAND flash memory device comprising: a substrate formed of a semiconducting material, the substrate having an intermediate substrate region free from any source/drain region; at least first and second vertical pillars each including a plurality of memory cells, and the second vertical pillar being adjacent to the first vertical pillar, and the first vertical pillar including a first body portion, a first bottom portion and a first top portion, and the second vertical pillar including a second body portion, a second bottom portion and a second top portion, and the first and second body portions being in contact with the substrate and comprised of first and second semiconductor films respectively, and the first and second bottom portions also being in contact with the substrate, and the intermediate substrate region of the substrate being located between the first and second bottom portions; a first gate electrode that is not a part of a memory cell, the first gate electrode surrounding the first and second bottom portions such that the first and second body portions each penetrate the first gate electrode, and the first gate electrode being located on at least the intermediate substrate region with only a gate dielectric intervening between the first gate electrode and the intermediate substrate region; and first and second source/drain regions, the first source/drain region being located at the first top portion of the first vertical pillar, the second source/drain region being located at the second top portion of the second vertical pillar.
地址 Ottawa CA