AUXILIARY SELF-PROTECTING TRANSISTOR STRUCTURE

摘要

This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.

主权项

1. An auxiliary self-protecting transistor circuit, comprising:
an electrostatic discharge (ESD) device including a gate terminal, a drain terminal, and a source terminal, wherein the drain terminal of the ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, wherein the ESD device is configured to provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device to protect the CMOS transistor.