GROUP III-N TRANSISTORS ON NANOSCALE TEMPLATE STRUCTURES

摘要

A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

主权项

1. A III-N field effect transistor (FET), comprising:
first and second group III-N device layer stacks physically separated from one another and disposed above a silicon substrate, wherein each of the group III-N device layer stacks comprises a channel semiconductor layer; and a gate stack disposed over the III-N device layer stacks, adjacent sidewalls of each of the III-N device layer stacks, and below each of the III-N device layer stacks, wherein the gate stack anchors the III-N device layer stacks to the silicon substrate.