发明名称 |
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE |
摘要 |
A semiconductor device including a memory cell having a control gate electrode and a memory gate electrode formed via a charge accumulation layer with respect to the control gate electrode is provided which improves its performance. A control gate electrode which configures a memory cell, and a metallic film which configures part of the memory gate electrode are formed by a so-called gate last process. Thus, the memory gate electrode is configured by a silicon film corresponding to a p-type semiconductor film being in contact with an ONO film, and the metallic film. Further, a contact plug is coupled to both of the silicon film and the metallic film which configure the memory gate electrode. |
申请公布号 |
US2016064389(A1) |
申请公布日期 |
2016.03.03 |
申请号 |
US201514828473 |
申请日期 |
2015.08.17 |
申请人 |
Renesas Electronics Corporation |
发明人 |
Mihara Tatsuyoshi |
分类号 |
H01L27/115;H01L29/66;H01L29/792;H01L21/28 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
1. A method of manufacturing a semiconductor device equipped with a memory cell of a nonvolatile memory, comprising the steps of:
(a) providing a semiconductor substrate; (b) forming a first dummy gate electrode over the semiconductor substrate through a first insulating film; (c) forming in order a second insulating film having a charge accumulation part thereinside, a first semiconductor film and a second semiconductor film each having a p-type conductivity type, so as to cover sidewalls of the first dummy gate electrode and the semiconductor substrate exposed from the first insulating film in adjacency to the sidewalls; (d) processing the first semiconductor film and the second semiconductor film to thereby form a second dummy gate electrode including the first semiconductor film and the second semiconductor film over the sidewalls of the first dummy gate electrode through the second insulating film; (e) forming a first interlayer insulating film so as to cover the first dummy gate electrode and the second dummy gate electrode; (f) polishing the first interlayer insulating film to expose the first dummy gate electrode and the second dummy gate electrode; (g) removing the second semiconductor film configuring the second dummy gate electrode, and the first dummy gate electrode; (h) forming a first gate electrode corresponding to a metal gate electrode for the memory cell in a first trench corresponding to a region from which the first dummy gate electrode is removed in the (g) step, and forming a metallic film in a second trench corresponding to a region from which the second semiconductor film is removed in the (g) step to thereby form a second gate electrode including the first semiconductor film and the metallic film for the memory cell; |
地址 |
Tokyo JP |