| 摘要 |
Immediate values can be used to specify a target address of branch or jump instructions. In RISC architectures such as MIPS, only limited amounts of bits are used for the immediate value, e.g. 16 bits, while 64 bits may be required, depending on granularity. The problem is addressed by decoding a series of three instructions ATI, AHI, AUI that cause 48 bits of an arbitrary 64-bit immediate value to be constructed in a general purpose register GP1 and a fourth instruction that completes the 64-bit value and branches to or accesses a memory location determined using the 64-bit value in the register. This provides a separate instruction in an instruction set architecture for non-destructive writing of 16-bit portions of a 64 bit register. Also provided is directly addressing portions of the double-word sized memory space 100, where the ATI/AHI/AUI instructions add and shift immediate values to respective quartiles of GP1. |
