Memory circuitry including read voltage boost

摘要

Memory circuitry 2 includes an array 4 of bit cells 6. One or more boost capacitors C1, C2 are connected to bit lines 8 running through the array 4 and serve to store a sample charge with a sample voltage difference during a sampling configuration of the boost capacitors C1, C2. A boost configuration is subsequently adopted in which the boost capacitors C1, C2 are connected with a different plurality to respective bit lines 8 such that the sample voltage difference is added to the voltage change within the bit line produced by the bit line cell 6 so as to generate an increased magnitude change in voltage which is supplied to sense amplifier circuitry 12.

主权项

1. Memory circuitry comprising:
an array of bit cells comprising a plurality of columns of bit cells; a plurality of bit lines coupled to said plurality of columns of bit cells within said array; sense amplifier circuitry configured to sense a voltage change on at least one of said plurality of bit lines during a read operation; at least one boost capacitor; and boost control circuitry configured to couple said at least one boost capacitor to said at least one of said plurality of bit lines in one of a plurality of configurations including:
(i) a sampling configuration in which said at least one boost capacitor is coupled to said at least one of said plurality of bit lines with a first polarity and an initial voltage change upon said at least one of said plurality of bit lines during said read operation produces a sampled charge with a sampled voltage difference to be stored by said at least one boost capacitor; and(ii) a boost configuration in which said at least one boost capacitor is coupled to said at least one of said plurality of bit lines with a second polarity, said second polarity is a reverse of said first polarity, and said sampled voltage difference is added to said voltage change on said at least one of said plurality of bit lines and supplied to said sense amplifier circuitry.