Prefetching data

摘要

The present disclosure is directed towards a prefetch controller configured to communicate with a prefetch cache in order to increase system performance. In some embodiments, the prefetch controller may include an instruction lookup table (ILT) configured to receive a first tuple including a first instruction ID and a first missed data address. The prefetch controller may further include a tuple history queue (THQ) configured to receive an instruction/stride tuple, the instruction/stride tuple generated by subtracting a last data access address from the first missed data address. The prefetch controller may further include a sequence prediction table (SPT) in communication with the tuple history queue (THQ) and the instruction lookup table. The prefetch controller may also include an adder in communication with the instruction lookup table (ILT) and the sequence prediction table (SPT) configured to generate a predicted prefetch address and to provide the predicted prefetch address to a prefetch cache. Numerous other embodiments are also within the scope of the present disclosure.

主权项

1. A system comprising:
a data cache configured to store at least one instruction; a processor operatively connected to said data cache, said processor configured to execute said at least one instruction; a prefetch controller operatively connected with said data cache, said prefetch controller configured to
receive a first tuple including a first instruction ID and a first missed data address, said prefetch controller further configuredretrieve a last data access address and tosubtract said last data access address from said first missed data address to generate an instruction/stride tuple, said prefetch controller configured touse said instruction/stride tuple to generate a predicted prefetch address; and a prefetch cache configured to receive said predicted prefetch address from said prefetch controller and to provide said predicted prefetch address to said data cache.