Asynchronous programmable JTAG-based interface to debug any system-on-chip states, power modes, resets, clocks, and complex digital logic

摘要

An asynchronous debug interface is disclosed that allows TAG agents, JTAG-based debuggers, firmware, and software to debug, access, and override any functional registers, interrupt registers, power/clock gating enables, etc., of core logic being tested. The asynchronous debug interface works at a wide range of clock frequencies and allows read and write transactions to take place on a side channel, as well as within the on chip processor fabric without switching into a debug or test mode. The asynchronous debug interface works with two-wire and four-wire JTAG controller configurations, and is compliant with IEEE standards, such as 1149.1, 1149.7, etc., and provides an efficient and seamless way to debug complex system-on-chip states and system-on-chip products.

主权项

1. A system to asynchronously debug a core logic, the core logic comprising a central processing unit, a bus, and a functional clock, the system comprising:
an intelligence unit comprising a test program executed by a joint test action group-compliant (JTAG compliant) debugger, the JTAG compliant debugger to operate with a JTAG-compliant test access port (TAP) controller using a test clock, the test program to be run on the core logic through a JTAG interface in real time; a read interface to read from a register, a memory location, or an input/output (I/O) port of the core logic through a side channel; a write interface to write to the register, the memory location, or the I/O port of the core logic through the side channel; and a priority arbiter to arbitrate between access to the bus of the core logic by either the intelligence unit or circuitry within the core logic;wherein a predetermined number of idle states is sent to the core logic by the test program using the JTAG interface in between succeeding write operations to or read operations from the register, the memory location, or the I/O port of the core logic, wherein the succeeding write operations to or read operations from are taking place through the side channel.