Hybrid orientation fin field effect transistor and planar field effect transistor

摘要

A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.

主权项

1. A semiconductor structure comprising:
a fin field effect transistor located on a first portion of a lower insulator layer, said fin field effect transistor comprising at least one semiconductor fin and a first gate stack, wherein each of said at least one semiconductor fin has a first width and comprises a fin source region, a fin drain region, and a fin body region laterally surrounded by said fin source region and said fin drain region, and said first gate stack comprises a first gate dielectric and a first gate electrode and straddles each of said at least one semiconductor fin; a planar field effect transistor located on a stack, from bottom to top, of a second portion of said lower insulator layer, a buried semiconductor layer, and an upper insulator layer, said planar field effect transistor comprising a top semiconductor portion and a second gate stack, wherein said top semiconductor portion has a second width greater than said first width and comprises a planar source region, a planar drain region, and a planar body region laterally surrounded by said planar source region and said planar drain region, and said second gate stack comprises a second gate dielectric and a second gate electrode and straddles said top semiconductor portion; and a planarization dielectric layer having a planar top surface located over said fin field effect transistor, said planar field effect transistor and exposed surfaces of said lower insulator layer and a bottom surface contacting said lower insulator layer, wherein a first vertical distance from an interface between said first gate electrode and a topmost surface of said first gate dielectric to a topmost surface of said first gate electrode is substantially the same as a second vertical distance from an interface between said second gate electrode and said second gate dielectric to a topmost surface of said second gate electrode.