System and method for simplifying cache coherence using multiple write policies

摘要

System and methods for cache coherence in a multi-core processing environment having a local/shared cache hierarchy. The system includes multiple processor cores, a main memory, and a local cache memory associated with each core for storing cache lines accessible only by the associated core. Cache lines are classified as either private or shared. A shared cache memory is coupled to the local cache memories and main memory for storing cache lines. The cores follow a write-back to the local memory for private cache lines, and a write-through to the shared memory for shared cache lines. Shared cache lines in local cache memory enter a transient dirty state when written by the core. Shared cache lines transition from a transient dirty to a valid state with a self-initiated write-through to the shared memory. The write-through to shared memory can include only data that was modified in the transient dirty state.

主权项

1. A computer system comprising:
multiple processor cores; a main memory; at least one local cache memory associated with and operatively coupled to each core for storing cache lines accessible only by the associated core, each of the cache lines being classified as either a shared cache line or a private cache line; and a global cache memory, the global cache memory being operatively coupled to the local cache memories and main memory and accessible by the cores, the global cache memory being capable of storing a plurality of cache lines, and wherein when a core writes a cache line, the core performs a write-back to the associated local cache memory if the cache line is a private cache line and a write-through to the global cache memory if the cache line is a shared cache line, wherein at least one of the shared cache lines are in a valid state, an invalid state, or a transient dirty state, and wherein a shared cache line in a local cache memory transitions to the transient dirty state from the valid state or the invalid state when the cache line is written by the associated core, and wherein a shared cache line in the transient dirty state transitions to the valid state with a self-initiated write-through to the global cache memory.