| 主权项 |
1. An apparatus comprising:
a memory die including dynamic random access memory (DRAM), a mode register including a storage location for a thermal offset bit, and a memory thermal sensor; and a second die including logic circuitry thermally coupled with the memory die, the second die further including a first thermal sensor and a second thermal sensor, the first and second thermal sensors to detect a thermal gradient, and the logic circuitry to provide a thermal offset bit to the storage location for the thermal offset bit of the mode register on the memory die responsive to detection of a change in the thermal gradient, the memory thermal sensor of the memory die being aligned with or in close proximity with the first thermal sensor of the second die, and the second thermal sensor of the second die being located at a hot spot of the second die; wherein the memory die includes a temperature compensated self-refresh (TCSR) logic, the TCSR logic to modify a self-refresh rate of the DRAM responsive, at least in part, to the thermal offset bit. |
