发明名称 LOGIC CIRCUIT AND SYSTEM AND COMPUTER PROGRAM PRODUCT FOR LOGIC SYNTHESIS
摘要 A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.
申请公布号 US2016055270(A1) 申请公布日期 2016.02.25
申请号 US201414464366 申请日期 2014.08.20
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ;NATIONAL TAIWAN UNIVERSITY 发明人 CHUANG Chi-Chuan;LAI Yi-Hsiang;CHIANG Jie-Hong
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A logic circuit, comprising: at least one first input; at least one second input; an output; an input acknowledgement node configured to be coupled to a next logic stage; an output acknowledgement node configured to be coupled to a previous logic stage; a logic evaluation block coupled to the at least one first input, the at least one second input, and the output, the logic evaluation block configured to perform a logic evaluation of first and second input signals at the corresponding at least one first input and at least one second input, and to output an output signal corresponding to a result of the logic evaluation; a pre-charging circuit coupled to the at least one first input, the input acknowledgement node, and the logic evaluation block, the pre-charging circuit configured to pre-charge the logic evaluation block in response to the first input signal and a next stage acknowledgement signal at the input acknowledgement node; and a completion detection circuit coupled to the at least one second input, the output, and the output acknowledgement node, the completion detection circuit configured to generate a previous stage acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.
地址 Hsinchu TW