| 主权项 |
1. A shift register comprising a plurality of stages of shift register circuit, wherein each stage of shift register circuit comprises:
a first switch having a first terminal for receiving a first clock signal, a second terminal for outputting a scan signal of a current stage of shift register circuit, and a control terminal electrically coupled to a node of the current stage of shift register circuit; an input circuit for pulling up a voltage level of the node of the shift register circuit according to a scan signal of a shift register circuit that is one stage before the current stage of shift register circuit; a pull-down circuit electrically coupled to a second system voltage terminal, the node of the current stage of shift register circuit and the second terminal of the first switch, the pull-down circuit for pulling down the voltage level of the node of the current stage of shift register circuit and a voltage level of the second terminal of the first switch according to a scan signal of a shift register circuit that is one stage after the current stage of shift register circuit; and a ripple reduction circuit electrically coupled to the node of the current stage of shift register circuit and a first system voltage terminal, the ripple reduction circuit for receiving a second clock signal and suppressing ripples on the node of the current stage of shift register circuit and ripples on the scan signal of the current stage of shift register circuit caused by the first clock coupling; wherein the first clock signal and the second clock signal have a same period but opposite phases. |
