Procedimiento y aparato para habilitar la señalización cooperativa de una interrupción de bus compartido en un sub-sistema de memoria de rangos múltiples

摘要

A memory system (104) is disclosed. The memory system includes first (508a) and second (510a) memory devices, and a memory controller (502) configured to selectively enable one of the memory devices, the memory controller having a first line (601) coupled to the first and second memory devices and a second line (602) coupled to the first and second memory devices. The first memory device is configured to provide a notification to the memory controller on the first line and the second memory device is configured to provide a notification to the memory controller on the second line. The first memory device is further configured not to load the first line and the second memory device is further configured not to load the second line when the memory controller is writing to the enabled memory device.