发明名称 |
Diode biased ESD protection device and method |
摘要 |
An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region. |
申请公布号 |
US9263428(B2) |
申请公布日期 |
2016.02.16 |
申请号 |
US201313910071 |
申请日期 |
2013.06.04 |
申请人 |
Infineon Technologies AG |
发明人 |
Russ Cornelius Christian;Alvarez David |
分类号 |
H01L23/62;H01L27/02;H01L21/8234 |
主分类号 |
H01L23/62 |
代理机构 |
Slater & Matsil, L.L.P. |
代理人 |
Slater & Matsil, L.L.P. |
主权项 |
1. An electrostatic discharge (ESD) protection device comprising:
an MOS transistor comprising a gate, a drain, and a source disposed in a first semiconductor region; a node designated for ESD protection electrically connected to the drain; an internal parasitic capacitance coupled between the gate and the drain; a p+/n+ diode coupled between the gate and source and disposed in a second semiconductor region within the first semiconductor region; and a complimentary p+/n+ diode coupled between the gate and source and disposed in a third semiconductor region within the first semiconductor region, wherein the p+/n+ diode and the complimentary p+/n+ diode are symmetrically located on opposite sides of the source, wherein the p+/n+ diode and the complimentary p+/n+ diode would be reverse biased if the MOS transistor were in an active operating region, wherein the gate is isolated from all other nodes except the internal parasitic capacitance, the p+/n+ diode, and the complimentary p+/n+ diode. |
地址 |
Neubiberg DE |