Method, apparatus and system for measuring latency in a physical unit of a circuit

摘要

In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

主权项

1. An apparatus comprising:
a physical layer unit (PHY) to be coupled to a serial link, the PHY comprising:
a receiver path to process data that is to be received via the serial link, wherein the receiver path is to include at least one fixed latency stage that is to be associated with a fixed latency and at least one variable latency stage;variable latency logic to determine a metric that is to be associated with the at least one variable latency stage; andPHY latency logic to determine a PHY latency for the receiver path based on the fixed latency and the metric.