TIMED MULTIPLEX SENSING

摘要

Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.

主权项

1. An apparatus, comprising:
a plurality of memory cells including a first memory cell connected to a first bit line and a second memory cell connected to a second bit line; one or more managing circuits configured to determine a first sensing time associated with the first memory cell and determine a second sensing time associated with the second memory cell; and a read circuit in communication with the first bit line and the second bit line, the read circuit configured to integrate a first current associated with the first bit line during the first sensing time and integrate a second current associated with the second bit line during the second sensing time, the read circuit configured to detect a first state of the first memory cell based on the integration of the first current and a reference voltage using a detection block during a first time period, the read circuit configured to detect a second state of the second memory cell based on the integration of the second current and the reference voltage using the detection block during a second time period subsequent to the first time period.