发明名称 METHOD FOR MANUFACTURING CMOS STRUCTURE
摘要 The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.
申请公布号 US2016043005(A1) 申请公布日期 2016.02.11
申请号 US201514823224 申请日期 2015.08.11
申请人 Silergy Semiconductor Technology (Hangzhou) Ltd. 发明人 You Budong;Lyu Zheng;Huang Xianguo;Peng Chuan
分类号 H01L21/8238;H01L29/417;H01L29/66;H01L29/06 主分类号 H01L21/8238
代理机构 代理人
主权项 1. A method for manufacturing a CMOS structure, comprising: forming shallow trench isolation in a semiconductor substrate, for defining a first region for a first MOSFET and a second MOSFET of a first type and for defining a second region for a third MOSFET and a fourth MOSFET of a second type; and forming a first to a fourth gate stacks on said semiconductor substrate, wherein said first gate stack and said second gate stack are disposed in said first region, and said third gate stack and said fourth gate stacks are disposed in said second region, each of said first to said fourth gate stacks comprises a gate conductor and a gate dielectric, and said gate dielectric is disposed between said gate conductor and said semiconductor substrate, said gate dielectrics of said first and third gate stacks have a first thickness, and said gate dielectrics of said second and fourth gate stacks have a second thickness larger than said first thickness.
地址 Hangzhou CN