发明名称 SCHOTTKY DIODE WITH BURIED LAYER IN GAN MATERIALS
摘要 A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.
申请公布号 US2016043198(A1) 申请公布日期 2016.02.11
申请号 US201514923139 申请日期 2015.10.26
申请人 Avogy, Inc. 发明人 Edwards Andrew;Nie Hui;Kizilyalli Isik C.;Brown Richard J.;Bour David P.;Romano Linda;Prunty Thomas R.
分类号 H01L29/66;H01L29/06;H01L29/20 主分类号 H01L29/66
代理机构 代理人
主权项 1. A method of fabricating a diode in gallium nitride (GaN) materials, the method comprising: providing a n-type GaN substrate having a first surface and a second surface; forming a first n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate; forming a p-type GaN epitaxial layer coupled to the first n-type GaN epitaxial layer; removing at least a portion of the p-type GaN epitaxial layer to form a plurality of p-type device structures; forming a second n-type GaN epitaxial layer coupled to the plurality of p-type device structures; removing at least a portion of the second n-type GaN epitaxial layer to expose a portion of at least one p-type device structure; and forming a first metallic structure electrically coupled to the exposed portion of the at least one p-type device structure and a remaining portion of the second n-type GaN epitaxial layer, wherein the first metallic structure is formed without prior cleaning and without prior annealing of the at least one p-type device structure and a remaining portion of the second n-type GaN epitaxial layer.
地址 San Jose CA US
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