发明名称 多層配線基板及びその製造方法
摘要 To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.
申请公布号 JP5855905(B2) 申请公布日期 2016.02.09
申请号 JP20110240394 申请日期 2011.11.01
申请人 日本特殊陶業株式会社 发明人 前田 真之介
分类号 H05K3/46;H05K3/00;H05K3/38 主分类号 H05K3/46
代理机构 代理人
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