Testing structure and method for interface trap density of gate oxide

摘要

The present invention discloses a testing structure and method for interface trap density of gate oxide, relating to the field of quality and reliability researches of MOS devices. The present invention makes the interface traps density tests for gate oxide layers of n-type and p-type MOS devices completed on a same testing structure, this does not only shorten the measurement period by half but also decrease the costs for testing instruments, because the present testing method is based on a simple current-voltage scanning test without using equipments such as pulse generator required in conventional method. The testing results obtained according to the present invention are featured with spectral peak, which facilitates the data analysis and computation.

主权项

1. A testing structure for interface trap density of gate oxide layer, comprising a gate oxide layer testing portion of p-type MOS device and a gate oxide layer testing portion of n-type MOS device, wherein the two testing portions share a common gate.