Dual-input oscillator for redundant phase-locked loop (PLL) operation

摘要

An oscillator of a phase-locked loop (PLL) or frequency-locked loop (FLL) may include two inputs. The two inputs may include a first analog input and a second digital input. The second digital input may receive a digital signal setting a desired output clock frequency of the oscillator and/or indicating an approximate frequency of frequency range for output by the oscillator. The first analog input may receive a voltage representative of a desired frequency for the output clock frequency of the PLL or FLL to fine-tune the output frequency from the approximate frequency set by the second digital input. The first analog input may be generated from a master clock input signal. When the master clock input signal disappears, the second digital signal controls the output frequency of the oscillator to allow redundant operation of the PLL or FLL even when no master clock input signal is present.

主权项

1. An apparatus, comprising:
an oscillator, comprising:
a clock output node configured to output a clock signal generated by the oscillator;an analog input node configured to receive an analog signal representative of a desired clock frequency for the clock signal;a digital input node configured to receive a digital signal corresponding to the desired clock frequency for the output clock signal; anda digital storage element coupled to the digital input node and configured to store at least one digital code corresponding to a clock frequency for the output clock signal, wherein the oscillator is configured to:
when the analog input signal is within a range defined by a high threshold and a low threshold indicating the analog input signal is present, generate the output clock signal based on a first combination of the analog input signal and the stored at least one digital code;when the analog input signal is outside the range:
disregard the analog input signal; andgenerate the output clock signal based on a second combination of the stored at least one digital code and a predetermined signal applied at the analog input node; a digital code generator coupled to the second input node and configured to generate the digital code corresponding to the desired clock frequency for the output clock signal, wherein the digital code is mapped to a particular clock frequency for output by the oscillator; and a loop filter coupled to the oscillator, wherein the loop filter is configured to operate at a second bandwidth different from a first higher bandwidth and a second phase margin different from a lower first phase margin when the analog input signal is outside the range.