Multi-port memory cell

摘要

A circuit includes a first data line, a second data line, a reference node, and a memory cell. The reference node is configured to have a reference voltage level corresponding to a first logical value. The memory cell includes a data node, a first transistor and a second transistor connected in series between the first data line and the reference node, and a third transistor between the data node and the second data line. A gate of the first transistor is coupled to the data node, and the first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value.

主权项

1. A circuit, comprising:
a reference node configured to have a reference voltage level corresponding to a first logical value; a memory cell, comprising: a data node; a first pass gate; a second pass gate; and a transistor having a drain, a source, and a gate, the gate of the transistor being coupled with the data node of the memory cell, and the source of the transistor being coupled with the reference node; a first data line, the first pass gate of the memory cell being between the drain of the transistor and the first data line; a second data line, the second pass gate of the memory cell being between the data node of the memory cell and the second data line; and a precharging unit configured to cause the second data line to have a predetermined voltage level corresponding to the first logical value.